As central processing units for computer systems have undergone constant improvement, the number of bits supported by and the processing speeds for computer systems have continued to increase. With increased processing power remaining a valuable feature for computer systems, matching the improvement in other computer system components has occasionally been difficult. Included in these components is a semiconductor memory component, such as random access memory (RAM) for the computer system.
Usual attempts to improve the RAM of a computer system involve increases in the amount of RAM in the system. Developers attempt to provide a maximum amount of RAM with minimum area consumption. Although the decrease in transistor size has allowed greater density in RAM circuits, the total area does increase, causing the percentage of good die per wafer to decrease. Thus, the ability to repair defective portions of a die becomes more important.
Memory chips typically employ redundancy to supply spare rows/columns of memory cells on the die. The redundant row/columns suitably aid in maintaining higher yield of working die and compensate for processing defects in the die by replacing defective rows/columns. In order to implement the use of the redundant row/columns, the chip is usually programmed with fuses to select the redundant row/column in place of the defective row/column.
Once the defective row/column has been identified, its address is typically programmed for the redundant circuitry in order to allow proper operation of the RAM and rerouting to the redundant circuitry for subsequent selections of the address of the defective row/column. Preprogramming of the redundant circuitry to act as a replacement for the defective row/column typically involves circuitry as shown in FIG. 1. For each address bit transistor 10, e.g., ADD1 to ADDn, there is an associated inverse address bit transistor 12, e.g., ADD1b to ADDnb. Each transistor 10 or 12 further has an associated fuse 14. To program the defective address for the redundant row/column, either the address bit transistor 10 or inverse address bit transistor 12 is deactivated by blowing an appropriate fuse 14.
For each subsequent selection of the defective address, the circuitry of FIG. 1 suitably produces a high voltage output signal, MATCH.sub.-- ALL, to allow selection of the redundant row/column in place of the defective row/column. However, for each incoming address signal that does not match the defective address, there is at least one current path to ground in the redundant circuitry of FIG. 1. Unfortunately, having a current path draws power, which becomes significant as the number of address bits increases. Further, increases in the number of address bits adds to the size of the circuitry by requiring more signal lines transmitting the address bits and their inverses. Another drawback of this circuitry is that the address signal lines have large capacitive loading even when the redundancy feature has not yet been activated. This drawback leads to greater power consumption and degradation of the speed performance of the chip.
Accordingly, a need exists for improved redundancy programming circuitry that reduces power consumption, size, and speed performance degradation. The present invention addresses such a need.